A. Technical Field
The present invention is generally related to integrated circuit devices, and more specifically, but not by way of limitation, to microcontrollers and microcontroller data transports.
B. Background of the Invention
Microcontroller system designers today have a myriad of choices when it comes to selecting a microcontroller for a project, i.e., 8-bit, 16-bit, RISC, CISC, or something in between. In most cases, many criteria are considered during the selection process. For example, most designers take into consideration the price, performance, power, code density, development time, functional features, and even further migration path alternatives when choosing the proper microcontroller. To complicate the selection process, demands related to one criterion generally influence the options in the other areas. Factors that are critical in one application may have little or no importance in another. Consequently, there is no one microcontroller that is perfect for all projects. However, a modern microcontroller should be flexible or adapt to fit a variety of design constraints.
When integrating complex analog circuitry with high-performance digital blocks, the operating environment should be kept as quiet and noise-free as possible. However, the clocking and switching that occur in the digital circuits of a microcontroller core inject noise into the sensitive analog section. One of the more complex issues surrounding microcontrollers is the ability to achieve high microcontroller performance while minimizing clock noise that may adversely affect sensitive analog circuits.
For most existing microprocessors, an instruction requires several clock cycles to execute, thereby increasing the noise transmitted to the surrounding environment. For example, RISC microcontrollers execute simple instructions at high clock frequencies and utilize execution pipeline(s) to improve system throughput. However, pipelines could cause pipeline hazards, because the pipeline approach requires either a compiler to anticipate potential resource conflicts or built-in hardware to detect and handle pipeline problems. When a program branch occurs, the RISC CPU utilizes one or more clock cycles (depending on the depth of the pipeline) to divert program fetching to the target branch address and discard the instruction(s) already fetched. As such, at least one additional clock cycle is required to discard instructions, thereby decreasing performance and increasing power consumption. In addition, performance of most traditional RISC microcontrollers is limited by the number of registers available for user applications.
Therefore, there is a need for a microcontroller with increased efficiency that minimizes adverse effects to surrounding components.